The present invention relates generally to a clock signal generator and, more particularly, to the generation of clock signals for memory devices or for synchronous interfaces such as communications interfaces.
In a system where a memory controller is connected to one or more memory devices (such as dual data rate (DDR) or static random access (SRAM) memory) via an interface, the memory controller generates a clock signal for the memory interface. All other interface signals (such as addresses, data and command signals) that are sent from the memory controller over the interface to the memory device(s) are synchronous with this clock signal.
The memory devices require specific and precise timing at their data, address and clock inputs. As typical memory boards have dense routing in terms of numerous wires, providing suitable and exact timing of the data and address signals, as well as the corresponding clock signals, places a high requirement on the memory interface. If the memory interface fails to meet the requirements, the timing at the inputs to the memory devices may be different from the timing at the corresponding outputs of the controlling devices, which may impair the overall performance of the memory systems.
In order to satisfy the timing requirements, conventional solutions shift the phase of the clock signals. Some known solutions employ phase locked loops (PLL) with phase mixers or delay locked loops (DLL) to optimize the phase relationship of a clock signal with regard to a data signal. However, PLLs and DLLs consume a considerable amount of silicon area and power and are time-consuming to characterize. Further, PLLs and DLLs are frequency band dependent and so cannot be used outside a specified frequency range. Other known solutions use shift registers to achieve a phase shift. However, when different clock division ratios are required, this necessitates increasing the number of flip-flops and therefore, silicon area and power requirements. Another known arrangement employs a clock divider counter value, comparator and a combination of latches and logic gates to phase shift a divided base clock signal. However, this arrangement cannot generate a clock signal with a 50% duty cycle nor can it be used for dual data rate interfaces which require that both edges of the clock signal are evenly placed for launching data on both rising and falling edges of the clock.
Thus it would be advantageous to provide an apparatus for generating a clock signal that mitigated at least some of the above-mentioned disadvantages of the known systems.